• DocumentCode
    3133374
  • Title

    Test compression and logic BIST at your fingertips

  • Author

    Wu, Shianling ; Wang, Laung-Terng ; Cho, Jin Woo ; Jiang, Zhigang ; Sheu, Boryau

  • fYear
    2005
  • fDate
    8-8 Nov. 2005
  • Lastpage
    1285
  • Abstract
    This paper describes two design-for-test (DFT) methods that provide flexibility in order to achieve desired test cost reduction goal using embedded scan compression and logic built-in self-test (BIST). In some applications, one method can be used in conjunction with the other
  • Keywords
    built-in self test; design for testability; integrated circuit design; DFT; design-for-test; embedded scan compression; logic BIST; logic built-in self-test; test compression; Automatic testing; Broadcasting; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Delay; Design for testability; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2005. Proceedings. ITC 2005. IEEE International
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-9038-5
  • Type

    conf

  • DOI
    10.1109/TEST.2005.1584111
  • Filename
    1584111
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3133374