Automatic generation of a simulation compiler by a HW/SW codesign system

An ISA (instruction set architecture) simulator is an indispensable tool for the design, development and customization of new processors. ISA simulators provide various features such as checking instruction behavior and/or estimating performance and chip size for a target processor. Due to the increasing complexity of chip architecture and time to market pressure, performance becomes one of the most important features for ISA simulators. This paper describes a technique for automatic generation of a simulation compiler that translates a target code into a host code, by a HW/SW codesign system. We proposed an indirect approach for the simulation compiler; whereby, an execution file of a target processor is modeled in the C language and translated into the execution file of the host machine using a compiler. An advantage of our approach is the ability of the compiler on the host machine to easily translate a target code into host codes.