DocumentCode :
3133381
Title :
Encounter test OPMISR/sup +/ on-chip compression
Author :
Keller, Brion
Author_Institution :
Cadence Design Syst., Endicott, NY
fYear :
2005
fDate :
8-8 Nov. 2005
Lastpage :
1287
Abstract :
As technology progresses, chips push on all automated test equipment (ATE) cost variables: speed, pin count, and test buffer size. In response to the challenges of testing these ever-larger chips, all of the major ATPG vendors have come out with products that compress test data volume and reduce test time - OPMISR: simple, effective output compression. While OPMISR can provide a substantial data volume reduction, it is limited to about 50% reduction in test application time. An alternative implementation of OPMISR, OPMISR+, was being employed at the Cadence Encounter Test product. OPMISR+ can easily provide greater than 100 times test data volume reduction in addition to 40 times or more scan test time reduction. This paper gives an example of its scan configuration
Keywords :
automatic test equipment; automatic test pattern generation; integrated circuit testing; ATPG vendors; OPMISR; automated test equipment; compress test data volume; encounter test; on-chip compression; output compression; scan configuration; Automatic test pattern generation; Automatic testing; Buffer storage; Built-in self-test; Costs; Delay; Logic testing; Pins; System testing; Test equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
Type :
conf
DOI :
10.1109/TEST.2005.1584112
Filename :
1584112
Link To Document :
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