DocumentCode
3133440
Title
Application of fast layout synthesis environment to dividers evaluation
Author
Houelle, A. ; Mehrez, H. ; Vaucher, N. ; Montalvo, L. ; Guyot, A.
Author_Institution
MASI CAO-VLSI Lab., Univ. Pierre et Marie Curie, Paris, France
fYear
1995
fDate
19-21 Jul 1995
Firstpage
67
Lastpage
74
Abstract
Experience has shown that generator programs are quite often written by VLSI designers, as they hold the empirical knowledge better than anyone. However, their ability does not necessarily include programming and debugging skills: these designers have to focus on the problem at hand not on the tools or the language they use to solve it. GenOptim has been created to quickly design efficient IEEE 754 floating-point macro-cell generators that do not rely on particular target technologies. Whereas the design of fast and efficient adders, multipliers and shifters is well understood division and square root remain a serious design challenge. GenOptim was used to quickly evaluate new divider architectures
Keywords
dividing circuits; floating point arithmetic; programming environments; GenOptim; IEEE 754 floating-point macro-cell generators; dividers evaluation; division; generator programs; layout synthesis environment; square root; Adders; Circuit synthesis; Circuit testing; Debugging; Driver circuits; Equations; Libraries; Logic; Very large scale integration; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Arithmetic, 1995., Proceedings of the 12th Symposium on
Conference_Location
Bath
Print_ISBN
0-8186-7089-4
Type
conf
DOI
10.1109/ARITH.1995.465375
Filename
465375
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