Title :
Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"
Author :
Chelstrom, Nathan
Author_Institution :
IBM, Austin, TX
Abstract :
With a growing number of system-on-chip (SoC) and multi-core products entering the marketplace, innovative solutions have been created to overcome the challenges these products bring in terms of testability. Some of the challenges associated with SoC and multi-core testing are related to scan test, memory test, asynchronous interface, debug, and tester related challenges. This paper describes the particular ways the CELL processor has overcome these challenges
Keywords :
asynchronous circuits; integrated circuit testing; system-on-chip; CELL processor; asynchronous interface; memory test; multicore testing; scan test; system-on-chip testing; Clocks; Cost function; Logic arrays; Logic design; Logic testing; Process design; Semiconductor device testing; Silicon; System testing; System-on-a-chip;
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
DOI :
10.1109/TEST.2005.1584117
