DocumentCode :
3133489
Title :
Today´s SOC test challenges
Author :
Zorian, Yervant
Author_Institution :
Virage Logic Corp., Fremont, CA
fYear :
2005
fDate :
8-8 Nov. 2005
Lastpage :
1302
Abstract :
A set of SoC test challenges have been introduced a decade ago, as embedded core based design and hence multi-core SoCs started to become popular. The topic of this panel is to analyze the SoC test challenges and determine if they have already been solved or not
Keywords :
embedded systems; integrated circuit testing; system-on-chip; embedded cores; system-on-chip testing; Built-in self-test; Design engineering; Design for testability; Job shop scheduling; Logic design; Logic testing; Manufacturing; Redundancy; Silicon; Test equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-9038-5
Type :
conf
DOI :
10.1109/TEST.2005.1584120
Filename :
1584120
Link To Document :
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