DocumentCode :
3133529
Title :
Impact of test structure design on electromigration of metal interconnect
Author :
Qiang, Guo ; Foo, Lo Keng ; Xu, Zeng ; Pei, Yao ; Ping, Neo Soh
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore
fYear :
1999
fDate :
1999
Firstpage :
39
Lastpage :
43
Abstract :
The impact of test structure design on the electromigration (EM) lifetime of metal interconnects has been investigated using high resolution resistance measurement (HRRM). The metal stripe in the test structure is of bamboo structure and multiple vias are added at both ends of the line to enhance the via effect. The resistance change of the test structure clearly shows two stages in the EM test. The values of activation energy Ea in stage II are found to be much smaller than that of bulk diffusion; rather, they are quite close to those obtained in wide polycrystalline stripes. Moreover, line electromigration becomes easier when more vias are added at the end of the line. These results indicate that W-plug vias not only cause discontinuity at the interface between metal and W-plug, but also make metal stripes near W-plug vias much more vulnerable to electromigration, which further reduces the electromigration lifetime of the metal stripe
Keywords :
diffusion; electric resistance measurement; electromigration; failure analysis; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; EM test stages; HRRM; W; W-plug vias; activation energy; bamboo structure; bulk diffusion; electromigration; electromigration lifetime; high resolution resistance measurement; interface discontinuity; line electromigration; metal interconnects; metal stripe; metal/W-plug interface; multiple vias; polycrystalline stripes; resistance change; test structure; test structure design; via effect; Bonding; Electrical resistance measurement; Electromigration; Life testing; Metallization; NIST; Performance evaluation; Temperature distribution; Tin; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the
Print_ISBN :
0-7803-5187-8
Type :
conf
DOI :
10.1109/IPFA.1999.791301
Filename :
791301
Link To Document :
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