Title :
A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization
Author :
Woo, M. ; Bhat, M. ; Craig, M. ; Kenkare, P. ; Wnag, X. ; Tolic, F. ; Chuang, H. ; Parihar, S. ; Schmidt, J. ; Terpolilli, L. ; Pena, Ruben ; Derr, D. ; Cave, N. ; Crabtree, P. ; Capetillo, M. ; Filipiak, S. ; Lii, T. ; Nagy, A. ; O´Meara, D. ; Vuong, T.
Author_Institution :
Process Technol Dev., Motorola Inc., Austin, TX, USA
Abstract :
In this work a 3.97 /spl mu/m/sup 2/ 6T CMOS SRAM bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization. This 0.20 /spl mu/m process technology is suitable for stand-alone SRAM applications as well as embedded applications such as digital signal processors. A stable bitcell operation has been demonstrated for power supply (Vdd) of 1.8 V. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.65 /spl mu/m.
Keywords :
CMOS memory circuits; SRAM chips; copper; integrated circuit interconnections; integrated circuit metallisation; 0.20 micron; 1.8 V; 6T bitcell; CMOS SRAM technology; Cu; copper interconnect metallization; digital signal processor; logic platform; self-aligned local interconnect; CMOS technology; Copper; Etching; Implants; Logic devices; MOSFET circuits; Metallization; Optical films; Printing; Random access memory;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689179
