DocumentCode :
3133692
Title :
A new DC voltage-voltage method to measure the interface traps in deep sub-micron MOS transistors
Author :
Jie, B.B. ; Li, M.-F. ; Chim, W.K. ; Chan, D.S.H. ; Lo, K.F.
Author_Institution :
Centre for Integrated Circuit Failure Analysis & Reliability, Nat. Univ. of Singapore, Singapore
fYear :
1999
fDate :
1999
Firstpage :
89
Lastpage :
93
Abstract :
A direct-current voltage-voltage (DCVV) technique for the measurement of stress-generated interface traps in sub-micron metal-oxide-semiconductor transistors (MOSTs) is demonstrated. This method uses the source-bulk-drain structure of a sub-micron MOST as an effective lateral bipolar transistor when the channel region is out of inversion under the control of the gate voltage Vgb. The emitter injects the minority carriers into the base region and the collector is open. The Vcb versus Vgb spectrum can be explained quantitatively using the extended Ebers-Moll equations and interface trap Shockley-Read-Hall (SRH) recombination. A single effective interface trap at the source or drain side could be detected, and interface traps at the source side can be separated from those at the drain side by the new method
Keywords :
MOSFET; electric potential; electron traps; electron-hole recombination; hole traps; interface states; minority carriers; semiconductor device measurement; DC voltage-voltage method; DCVV technique; MOS transistors; MOSTs; base region; channel region; direct-current voltage-voltage technique; drain side traps; effective lateral bipolar transistor; emitter minority carrier injection; extended Ebers-Moll equations; gate voltage; interface trap Shockley-Read-Hall recombination; interface traps; metal-oxide-semiconductor transistors; open collector; single effective interface trap; source side traps; source-bulk-drain structure; stress-generated interface trap measurement; Circuit testing; Failure analysis; Integrated circuit measurements; Integrated circuit reliability; MOSFET circuits; Manufacturing industries; Reliability engineering; Semiconductor device manufacture; Stress measurement; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the
Print_ISBN :
0-7803-5187-8
Type :
conf
DOI :
10.1109/IPFA.1999.791312
Filename :
791312
Link To Document :
بازگشت