Title :
Novel backside sample preparation processes for advanced CMOS integrated circuits failure analysis
Author :
Chew, Y.Y. ; Siek, K.H. ; Yee, W.M.
Author_Institution :
Dept. for Quality & Reliability, Intel Technol. Sdn. Bhd., Penang, Malaysia
Abstract :
Backside sample preparation techniques are reported for advanced integrated circuits (ICs) packaged in conventional wire-bond ceramic and plastic packages as well as in flip-chip packages. Backside sample preparation is an enabling step to other backside FA techniques such as infrared (IR) emission microscopy and IR-based internal signal voltage probing. The sample preparation steps involve heat sink/package milling, and silicon substrate thinning and polishing. In addition, the use of an antireflection coating (ARC) layer to improve the success rate and sensitivity of backside photo-emission microscopy is presented
Keywords :
CMOS integrated circuits; antireflection coatings; ceramic packaging; failure analysis; heat sinks; integrated circuit packaging; integrated circuit testing; lead bonding; machining; optical microscopy; plastic packaging; polishing; specimen preparation; thermal management (packaging); CMOS integrated circuits failure analysis; IC package; IR emission microscopy; IR-based internal signal voltage probing; Si; antireflection coating; backside FA techniques; backside photo-emission microscopy; backside sample preparation processes; backside sample preparation techniques; flip-chip packages; heat sink milling; integrated circuits; package milling; plastic packages; sample preparation; sensitivity; silicon substrate polishing; silicon substrate thinning; success rate; wire-bond ceramic packages; CMOS process; Ceramics; Coatings; Heat sinks; Integrated circuit packaging; Microscopy; Milling; Plastic integrated circuit packaging; Silicon; Voltage;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the
Print_ISBN :
0-7803-5187-8
DOI :
10.1109/IPFA.1999.791318
