DocumentCode :
3133807
Title :
Identification of processing defects by focused ion beam (FIB) induced voltage contrast
Author :
Liu, Chun-Sheng ; Chen, Chih-Rong ; Hsieh, Yong-Fen
Author_Institution :
United Microelectron. Corp., Hsin-Chu, Taiwan
fYear :
1999
fDate :
1999
Firstpage :
128
Lastpage :
131
Abstract :
Processing defects related to multiple stacked metal via and/or contact structures were very difficult to verify to be a high resistance open issue or a bridge/leakage short issue. In this paper, FIB passive voltage contrast was very successfully implemented in 2 Mb SRAM debug to differentiate the two failure mechanisms, high via and/or contact resistance versus substrate defect-induced junction leakage. It was demonstrated in four different cases that passive voltage contrast was used to reveal and locate the specific failure site and followed with pinpoint diagnosis of the abnormality by TEM. It was also known that these defects were invisible to optical microscopy and SEM. The 2Mb SRAM process was a 0.25 μm, three-metal single-poly, 8-inch technology. Shallow trench isolation (STI), self-aligned TiSi2 silicide (salicide), and triple stacked W-plug processes were integrated in the manufacturing process. The failure mode and failure location were firstly identified by a MOSAID tester. Layer-by-layer deprocessing and top-view SEM examination were used for structural inspection at the failure site prior to FIB imaging. As soon as the fault was isolated by a passive voltage contrast comparison study, precision TEM analyses were utilized as the major tool for structural inspection in both plan-view and cross-section
Keywords :
SRAM chips; contact resistance; failure analysis; fault location; focused ion beam technology; inspection; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit testing; isolation technology; production testing; scanning electron microscopy; transmission electron microscopy; 0.25 micron; 2 Mbit; 8 in; FIB imaging; FIB induced voltage contrast; FIB passive voltage contrast; MOSAID tester; SEM; SRAM debug; SRAM process; STI; TEM; TiSi2; W; bridge/leakage short; contact resistance; contact structures; failure location; failure mechanisms; failure mode; failure site; fault isolation; focused ion beam induced voltage contrast; high resistance open; layer-by-layer deprocessing; manufacturing process; multiple stacked metal via structures; optical microscopy; passive voltage contrast; pinpoint diagnosis; processing defect identification; processing defects; salicide; self-aligned TiSi2 silicide; shallow trench isolation; structural inspection; substrate defect-induced junction leakage; three-metal single-poly technology; top-view SEM; triple stacked W-plug processes; via resistance; Bridge circuits; Contact resistance; Failure analysis; Focusing; Inspection; Ion beams; Optical microscopy; Random access memory; Scanning electron microscopy; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 1999. Proceedings of the 1999 7th International Symposium on the
Print_ISBN :
0-7803-5187-8
Type :
conf
DOI :
10.1109/IPFA.1999.791320
Filename :
791320
Link To Document :
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