Title :
1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells
Author :
Ohnakado, T. ; Ajika, N. ; Hayashi, H. ; Takada, H. ; Kobayashi, K. ; Sugahara, K. ; Satoh, S. ; Miyoshi, H.
Author_Institution :
Adv. Technol. R&D Center, Itami, Japan
Abstract :
A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast access operation.
Keywords :
bipolar transistor circuits; flash memories; low-power electronics; 1.5 V; bipolar transistor selected P-channel cell; cell current amplification; flash memory; nonword line boosting read; sector erase operation; Bipolar transistors; CMOS technology; Electronic equipment; Energy consumption; Flash memory; Flash memory cells; Laboratories; Research and development; Ultra large scale integration; Voltage;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689180
