Title :
Variable SYNC Signal Definition for Automata Performance Improvment
Author_Institution :
Fac. of Autom. Control & Comput. Eng., Tech. Univ. of Iasi
Abstract :
The present paper considers the problem of digital hazards that are present in combinatorial logic structures. My work is focused not on eliminating these hazards but on how to avoid and eventually use this unwanted feature when we are designing a digital automaton. The idea is to theoretically trace the output of the circuit implementing the next state functions of the automaton, determine the time frames when these outputs are logically correct and use those specific moments of time to provoke the automaton´s evolution towards the next correct state (according to the automaton´s states transitions graph). By doing so we shall drastically improve the working speed of the automaton we design
Keywords :
combinational circuits; finite automata; graph theory; hazards; logic testing; synchronisation; automata performance improvement; combinatorial logic structures; digital finite automaton design; digital hazards problem; states transitions graph; variable sync signal definition; Automata; Automatic control; Automatic logic units; Circuits; Clocks; Control engineering computing; Hazards; Signal design; Synchronization; Timing; Mealy automaton; combinatorial structures hazard; hazard analysis; variable duty factor clock;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277375
