Temperature distribution in power GaAs field effect transistors using spatially resolved photoluminescence mapping

In power FETs, channel temperature control is very important both in terms of output power and of operational lifetime, which is mainly determined by thermally activated degradation or failure mechanisms. This applies both for discrete devices and MMICs. The experimental approach currently relies on two methods, IR microscopy and liquid crystal thermography, but both are limited in terms of spatial resolution, causing them to fail when devices with sub-μm dimensions are considered. Also, these methods require some type of coating to be investigated, either with a material of known emissivity or with a liquid crystal layer whose uniformity may be difficult to control. Thermal resistance calculations are performed to assess channel temperature and therefore the expected MMIC reliability. In this approach, analytical thermal resistance models and FEA descriptions have been proposed. Use of thermal resistance assumes uniform temperature throughout the circuit, which is in general untrue due to the detailed geometrical bounding conditions, and also because of process imperfections which may occur. FEA descriptions in general rely on an assumption about the heat dissipation zone dimensions, which is very difficult to check experimentally. The purpose of this paper is thus twofold: first, to demonstrate a new methodology for accurate measurement and mapping of local channel temperatures in GaAs-based FETs based on spatially resolved photoluminescence spectroscopy, and second, to discuss FET behaviour as a function of gate voltage and to show that using thermal resistance to characterize channel temperature during aging tests is insufficient