DocumentCode :
3133994
Title :
Reducing the number of counters needed for integer multiplication
Author :
Owens, Robert M. ; Bajwa, Raminder S. ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear :
1995
fDate :
19-21 Jul 1995
Firstpage :
38
Lastpage :
41
Abstract :
In this paper we consider the problem of multiplying reasonably small integers using fewer counters than that required by straightforward partial product accumulation. Not surprisingly the method we use is based on the observation that integer multiplication can be formulated as aperiodic convolution. However, instead of using something like the Fast Fourier Transform to compute the aperiodic convolution, we use what are known as a “fast” convolution algorithms. In this way we can construct multipliers for as small as eighteen bit integers which use fewer counters than that required by straightforward partial product accumulation. Because of the perceived “overhead” involved with an aperiodic formulation of integer multiplication, the ability to do this goes somewhat against the conventional wisdom that aperiodic formulation of integer multiplication gains an advantage over a straightforward partial product formulation only for fairly large integers
Keywords :
counting circuits; digital arithmetic; multiplying circuits; aperiodic convolution; convolution algorithms; counters; fairly large integers; integer multiplication; partial product accumulation; partial product formulation; reasonably small integers; Computer science; Convolution; Cost function; Counting circuits; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Arithmetic, 1995., Proceedings of the 12th Symposium on
Conference_Location :
Bath
Print_ISBN :
0-8186-7089-4
Type :
conf
DOI :
10.1109/ARITH.1995.465379
Filename :
465379
Link To Document :
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