A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects

Author

Su, L. ; Schulz, R. ; Adkisson, J. ; Beyer, K. ; Biery, G. ; Cote, W. ; Crabbe, E. ; Edelstein, D. ; Ellis-Monaghan, J. ; Eld, E. ; Foster, D. ; Gehres, R. ; Goldblatt, R. ; Greco, N. ; Guenther, C. ; Heidenreich, J. ; Herman, J. ; Kiesling, D. ; Lin, L.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

9-11 June 1998

Firstpage

18

Lastpage

19

Abstract

A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including SRAM cell size down to 5.4 /spl mu/m/sup 2/ is combined with multiple threshold voltage devices and the first technology in the industry to offer copper interconnects. These features result in minimum unloaded inverter delay of 12.7 ps and enable microprocessor frequencies above 480 MHz.

Keywords

CMOS integrated circuits; SRAM chips; copper; integrated circuit interconnections; logic gates; microprocessor chips; 0.25 micron; 12.7 ps; 480 MHz; CMOS technology; SRAM; copper interconnect; groundrule scaling; inverter; microprocessor; multiple threshold voltage device; CMOS technology; Copper; Delay; Frequency; Inverters; Manufacturing industries; Metals industry; Microprocessors; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689182

Filename

689182