• DocumentCode
    3134243
  • Title

    Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design

  • Author

    Hong, R.C. ; Chang, G.W. ; Chao, C.Y. ; Chu, Y.B. ; Chen, C.I.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
  • fYear
    2010
  • fDate
    15-17 June 2010
  • Firstpage
    492
  • Lastpage
    497
  • Abstract
    This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.
  • Keywords
    active filters; digital signal processing chips; power harmonic filters; ADALINE; APF; DSP; compensation strategy; digital signal processor; hardware-in-the-loop simulation; harmonic compensation; nonlinear load; power factor; shunt active power filter design; three-phase source voltages; Active filters; Digital signal processing; Digital signal processors; Hardware; Power harmonic filters; Power system harmonics; Reactive power; Shunt (electrical); Virtual colonoscopy; Voltage; Active power filter; digital signal processor; hardware-in-the-loop; harmonics; real-time simulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference on
  • Conference_Location
    Taichung
  • Print_ISBN
    978-1-4244-5045-9
  • Electronic_ISBN
    978-1-4244-5046-6
  • Type

    conf

  • DOI
    10.1109/ICIEA.2010.5517124
  • Filename
    5517124