Design and implementation of wireless sensor node based on open core

Wireless sensor nodes are essential elements in wireless sensor networks. There are two important issues which need to be considered in order to build a sensor node: low power consumption and scalability. This paper proposes and presents a SoC architecture of wireless sensor node based on open source IP blocks such as OpenRISC 1200 microprocessor core and Wishbone Interconnect Matrix bus core. This hardware architecture is then verified in Altera Quartus II, and the power consumption and scalability of the hardware platform are assessed. At last, the whole system of the wireless sensor node is integrated on Altera DE2-70 FPGA board and its sensing, computation and wireless communication capabilities are verified.