Specialised architecture of dedicated hardware processors for real-time image data pre-processing

The conventional approach to video image processing is connected to many data transfers between video memory buffer and microprocessor units. Therefore, eliminating time consuming transfers and applying a pipelined image processing system seems to be a valuable solution. This architecture is particularly suitable for low level image processing. The author designed and built a specialised pipelined multiprocessor architecture for specialised hardware processors. A special, custom pipeline bus standard was designed to provide a convincing way of applying pipeline processors. The author designed and built some dedicated hardware processors in FPGA structure: median filter, logic processor, look-up-table processor, convolution processor and histogrammer. Dedicated hardware processor implementation in the Xilinx FPGA used other chips: FIFO buffers and Triple Port RAM