Title :
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Author :
Kozyrakis, Christoforos ; Patterson, David
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this paper, we use EEMBC, an industrial benchmark suite, to compare the VIRAM vector architecture to superscalar and VLIW processors for embedded multimedia applications. The comparison covers the VIRAM instruction set, vectorizing compiler and the prototype chip that integrates a vector processor with DRAM main memory. We demonstrate that executable code for VIRAM is up to 10 times smaller than VLIW code and comparable to ×86 CISC code. The simple, cache-less VIRAM chip is 2 times faster than a 4-way superscalar RISC processor that uses a 5 times faster clock frequency and consumes 10 times more power VIRAM is also 10 times faster than cache-based VLIW processors. Even after manual optimization of the VLIW code and insertion of SIMD and DSP instructions, the single-issue VIRAM processor is 60% faster than 5-way to 8-way VLIW designs.
Keywords :
computational complexity; embedded systems; parallel architectures; parallelising compilers; power consumption; reduced instruction set computing; CISC code; EEMBC; VIRAM vector architecture; VLIW architectures; cache-based VLIW processors; design complexity; embedded multimedia benchmarks; industrial benchmark suite; instruction set; superscalar RISC processor; superscalar architectures; vectorizing compiler; Clocks; Design optimization; Digital signal processing chips; Energy consumption; Frequency; Manuals; Prototypes; Reduced instruction set computing; VLIW; Vector processors;
Conference_Titel :
Microarchitecture, 2002. (MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on
Print_ISBN :
0-7695-1859-1
DOI :
10.1109/MICRO.2002.1176257