A 0.21 /spl mu/m/sup 2/ 7F/sup 2/ trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM

Author

Radens, C.J. ; Gruening, U. ; Weybright, M.E. ; DeBrosse, J.K. ; Kleinhenz, R.L. ; Hoenigschmid, H. ; Thomas, A.C. ; Mandelman, J.A. ; Alsmeier, J. ; Bronner, G.B.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

9-11 June 1998

Firstpage

36

Lastpage

37

Abstract

A 0.21 /spl mu/m/sup 2/ 7/sup F/2 trench capacitor DRAM cell with a locally-open globally-folded dual bitline has been fabricated using a 175 nm groundrule. This cell features a trench capacitor, a self-aligned trench-to-diffusion buried strap in direct proximity to the array transistor, shallow-trench device isolation (STI), a self-aligned poly-plug bitline contact, and two-levels of bitline wiring, both formed using a dual damascene process.

Keywords

DRAM chips; capacitors; integrated circuit metallisation; isolation technology; 1 Gbit; 175 nm; 4 Gbit; 7F/sup 2/ trench cell; DRAM; array transistor; dual damascene process; locally-open globally-folded dual bitline; self-aligned poly-plug bitline contact; self-aligned trench-to-diffusion buried strap; shallow trench isolation; trench capacitor; two-level bitline wiring; Capacitors; Optical device fabrication; Productivity; Random access memory; Research and development; Semiconductor device noise; Silicon compounds; Transistors; Wiring; X-ray lithography;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689189

Filename

689189