DocumentCode
3135561
Title
Compiling for instruction cache performance on a multithreaded architecture
Author
Kumar, Rakesh ; Tullsen, Dean M.
Author_Institution
University of California
fYear
2002
fDate
2002
Firstpage
419
Lastpage
429
Keywords
Communication system control; Computer architecture; Computer science; Hardware; Multithreading; Operating systems; Optimizing compilers; Program processors; Surface-mount technology; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 2002. (MICRO-35). Proceedings. 35th Annual IEEE/ACM International Symposium on
ISSN
1072-4451
Print_ISBN
0-7695-1859-1
Type
conf
DOI
10.1109/MICRO.2002.1176269
Filename
1176269
Link To Document