A novel pillar DRAM cell for 4 Gbit and beyond

A novel structure and fabrication process for a DRAM cell for 4 Gbit and beyond is proposed. A poly-Si pillar transistor is formed on top of a trench capacitor with the top of the pillar transistor being directly connected to the bit line. In order to reduce the process steps, word line formation by a spacer etch and self-aligned bit line contact using CMP process are developed. XTEM micrographs show almost single grain and less defect in the small pillars after crystallization annealing of prepatterned /spl alpha/-Si. Electrical measurements show that the pass transistor has good subthreshold slope and Id-Vd characteristics. Improvements in the device performance has been achieved by a sacrificial oxidation and hydrogenation.