Interconnect scaling: signal integrity and performance in future high-speed CMOS designs

Author

Sylvester, D. ; Chenming Hu ; Nakagawa, O.S. ; Soo-Young Oh

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1998

fDate

9-11 June 1998

Firstpage

42

Lastpage

43

Abstract

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 /spl mu/m generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.

Keywords

CMOS integrated circuits; ULSI; crosstalk; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; 0.25 to 0.07 micron; Cu; ULSI; aspect ratio; asymmetric pitch; copper; crosstalk; delay; driver; high-speed CMOS design; interconnect scaling; low-k dielectric; repeater; signal integrity; Clocks; Copper; Crosstalk; Delay; Dielectric materials; Integrated circuit interconnections; Repeaters; Signal design; Ultra large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689191

Filename

689191