Title :
A novel air gap integration scheme for multi-level interconnects using self-aligned via plugs
Author :
Ueda, T. ; Tamaoka, E. ; Yamashita, K. ; Aoi, N. ; Mayumi, S.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan
Abstract :
A novel multi-level interconnect process, realizing air gap structures composed of not new low k materials but conventional SiO/sub 2/ films, has been developed in order to drastically decrease the capacitance between lines. The effective relative dielectric constant of 1.8 is obtained. This process can solve the significant issues associated with air gap structure, such as the via failures due to misalignment between the line and via levels.
Keywords :
air gaps; capacitance; dielectric thin films; integrated circuit interconnections; permittivity; SiO/sub 2/; SiO/sub 2/ film; air gap integration; capacitance; dielectric constant; intermetal dielectric; multilevel interconnect; self-aligned via plug; Air gaps; Capacitance; Delay; Dielectric constant; Dielectric materials; Etching; Inorganic materials; Plugs; Thermal stability; Ultra large scale integration;
Conference_Titel :
VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4770-6
DOI :
10.1109/VLSIT.1998.689193
