A processor architecture for Horizon

Author

Thistle, Mark R. ; Smith, Burton J.

Author_Institution

Supercomput. Res. Center, Lanham, MD, USA

fYear

1988

fDate

14-18 Nov 1988

Firstpage

35

Lastpage

41

Abstract

Horizon is a scalable shared-memory multiple-instruction-stream-multiple-data-stream computer, currently under study, composed of a few hundred identical scalar processors and a comparable number of memories, sparsely embedded in a three-dimensional nearest-neighbor network. Each processor has a horizontal instruction set that can perform up to three floating-point operations per cycle without resorting to vector operations and will be capable performing at a rate of several hundred MFLOPS (millions of floating-point operations per second), to achieve an overall system performance target of 100 GFLOPS (billion of FLOPS). The architecture of the processor in the Horizon system is described

Keywords

parallel architectures; parallel machines; Horizon; floating-point operations; horizontal instruction set; processor architecture; scalable shared-memory MIMD computer; scalable shared-memory multiple-instruction-stream-multiple-data-stream computer; scalar processors; three-dimensional nearest-neighbor network; Bridges; Computer aided instruction; Computer architecture; Costs; Delay; Hardware; Pipelines; Supercomputers; System performance; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Supercomputing '88. [Vol.1]., Proceedings.

Conference_Location

Orlando, FL

Print_ISBN

0-8186-0882-X

Type

conf

DOI

10.1109/SUPERC.1988.44632

Filename

44632