VLSI implementation of an eight-state clustering based sequence equalizer

Author

Georgoulakis, K. ; Doumenis, D.G. ; Aggouras, G. ; Frantzeskakis, E.

Author_Institution

Wireless Commun. & Subscriber Syst., Intracom S.A., Peania Attika, Greece

Volume

2

fYear

1997

fDate

2-4 Jul 1997

Firstpage

1075

Abstract

This paper presents the VLSI implementation of a fixed, 8-state CBSE (clustering based sequence equalizer). Simulation results demonstrate superior performance compared to other types of equalizers, such as LTE, DFE and RBF. Furthermore, the architecture presented, does not exhibit performance degradations due to finite wordlength effects. The design was implemented on FPGA using approximately 24000 gates and it can accommodate transmission rates of up to 8 Mbps

Keywords

VLSI; cochannel interference; digital radio; equalisers; field programmable gate arrays; interference suppression; intersymbol interference; radio links; sequences; 8 Mbit/s; 8-state CBSE; FPGA; ISI; VLSI implementation; architecture; clustering based sequence equalizer; design; digital transmission radio link; eight-state clustering based sequence equalizer; finite wordlength effects; performance; simulation; transmission rates; Decision feedback equalizers; Degradation; Intersymbol interference; Least squares approximation; Maximum likelihood estimation; Nonlinear distortion; Receivers; SAW filters; Very large scale integration; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Signal Processing Proceedings, 1997. DSP 97., 1997 13th International Conference on

Conference_Location

Santorini

Print_ISBN

0-7803-4137-6

Type

conf

DOI

10.1109/ICDSP.1997.628551

Filename

628551