A perfect process compatible 2.49 /spl mu/m/sup 2/ embedded SRAM cell technology for 0.13 /spl mu/m-generation CMOS logic LSIs

Author

Sambonsugi, Y. ; Maruyama, T. ; Yano, K. ; Sakaue, H. ; Yamamoto, H. ; Kawamura, E. ; Ohkubo, S. ; Tamura, Y. ; Sugii, T.

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

1998

fDate

9-11 June 1998

Firstpage

62

Lastpage

63

Abstract

A high performance embedded SRAM technology for 0.13 μm logic LSIs has been developed. The memory cell size is 2.49 μm/sup 2/ which is the smallest of the 6Tr full-CMOS SRAMs. The concept of this technology is to provide perfect process compatibility with logic parts. This process includes Co salicide and gate/source/drain co-doping and excludes self-aligned contact and local-interconnect. A hole type sheared contact is used to reduce the number of contacts. We realized the stability of SRAM cell operation with as low as 1.0 V for low power application.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; VLSI; integrated circuit technology; large scale integration; 0.13 micron; 1 V; CMOS SRAMs; CMOS logic LSIs; Co salicide; CoSi; gate/source/drain co-doping; hole type sheared contact; low power application; memory cell operation stability; process compatible embedded SRAM cell technology; static RAM; CMOS logic circuits; CMOS process; CMOS technology; Contacts; Doping; Etching; Laboratories; Metallization; Random access memory; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4770-6

Type

conf

DOI

10.1109/VLSIT.1998.689199

Filename

689199