Title :
Triple-DES ASIC Module for a Power-Smart System-on-Chip Architecture
Author :
Patel, D. ; Muresan, R.
Author_Institution :
Sch. of Eng., Guelph Univ., Ont.
Abstract :
This paper presents new 3-DES architecture with current flattening support for increased resistance against power analysis attacks. Also, new pipelined architecture of the 3-DES algorithm is proposed and implemented using 0.18 mum CMOS technology. The paper presents synthesis and simulation results for the 3-DES ASIC implementation. The synthesis results have shown that 3-DES module occupies an area of 326K mum2 and the average power consumption is 18.35 mW. In comparison with previous research, the proposed implementation occupies less area and consumes less power. Other results presented include average current and power simulations results using Synopsys Nanosim tool
Keywords :
cryptography; logic design; low-power electronics; pipeline processing; system-on-chip; CMOS technology; average power consumption; pipelined architecture; power analysis attacks; power-smart system-on-chip architecture; triple-DES ASIC module; Application specific integrated circuits; CMOS technology; Cryptography; Data security; Embedded system; Energy consumption; Hardware; Information security; System-on-a-chip; Throughput; ASIC; Triple-DES; cryptosystem; power analysis attacks; power-smart system-on-chip;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277763
