• DocumentCode
    3138219
  • Title

    Accurate Simulation of Flip-Flop Timing Characteristics

  • Author

    Evans, David J.

  • Author_Institution
    Harris Electronic Systems Divisions, Melbourne, FL
  • fYear
    1978
  • fDate
    19-21 June 1978
  • Firstpage
    398
  • Lastpage
    404
  • Abstract
    Detailed timing analysis of flip-flops in a gate level simulator is described. The simulator detects violations of set-up time, hold time, and minimum clock, set, and reset pulse widths.
  • Keywords
    CMOS logic circuits; Circuit simulation; Clocks; Computational modeling; Flip-flops; Logic circuits; Logic devices; Propagation delay; Space vector pulse width modulation; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 1978. 15th Conference on
  • Type

    conf

  • DOI
    10.1109/DAC.1978.1585204
  • Filename
    1585204
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3138219