Title :
Accurate Simulation of Flip-Flop Timing Characteristics
Author_Institution :
Harris Electronic Systems Divisions, Melbourne, FL
Abstract :
Detailed timing analysis of flip-flops in a gate level simulator is described. The simulator detects violations of set-up time, hold time, and minimum clock, set, and reset pulse widths.
Keywords :
CMOS logic circuits; Circuit simulation; Clocks; Computational modeling; Flip-flops; Logic circuits; Logic devices; Propagation delay; Space vector pulse width modulation; Timing;
Conference_Titel :
Design Automation, 1978. 15th Conference on
DOI :
10.1109/DAC.1978.1585204
