Title :
A Module Level Simulation Technique for Systems Composed of LSI´s And MSI´s
Author :
Tokoro, Mario ; Sato, Masayuki ; Ishigami, Masayuki ; Tamura, Eiji ; Ishimitsu, Terunobu ; Ohara, Hisashi
Author_Institution :
Department of Electrical Engineering, Keio University, Yokohama, JAPAN
Abstract :
This paper describes newly developed techniques suitable for logic verification and fault simulation of digital systems which are mainly composed of LSI´s and MSI´s. A simulator employing such techniques has been implemented, and has shown definite advantages over existing simulators.
Keywords :
Circuit faults; Circuit simulation; Delay; Digital circuits; Digital systems; Hardware; Lamps; Large scale integration; Logic design; Timing;
Conference_Titel :
Design Automation, 1978. 15th Conference on
DOI :
10.1109/DAC.1978.1585206
