Arithmetic structures for inner-product and other computations based on a latency-free bit-serial multiplier design

Traditional bit-serial multipliers present one or more clock cycles of data latency. When combined with addition operations, as would be needed for an inner-product computation, the latency may increase further. We extend a design method for latency-free bit-serial multipliers to more powerful bit-serial arithmetic units capable of computing functions of the form S=VW+X, S=VW+X+Y, S=VW+X+Y+Z, S=VW+XY, and S=VW+XY+Z with no latency (i.e., with only combinational delay between input and output). We show that the above double multiplication and accumulative capabilities are obtained with small extra cost compared to simple bit-serial multipliers. More specifically, the added cost, contributed mainly by the use of a (7, 3) counter in lieu of a (5, 3) counter in each multiplier cell, is about 50% for the most complex unit, making our designs quite cost-effective. Unsigned or sign-extended 2´s-complement numbers may be used to produce arbitrarily long outputs. Since the designs are fully modular, they are easily introduced into VLSI libraries.