Title :
An Efficient Thread Recombining at Program Phase Changes
Author :
Sobue, Kazuki ; Tsumura, Tomoaki ; Matsuo, Hiroshi
Author_Institution :
Nagoya Inst. of Technol., Nagoya, Japan
Abstract :
Chip-multiprocessors now have become in wide use. For efficiently using the resources in chip-multiprocessors, programmers need to consider processor specifications and load balancing, but it is difficult for them. To address this problem, Thread Tailor has been proposed. Thread Tailor determines the number of threads based on processor specifications before execution, balances their loads based on the results of profiling and combines threads. However, Thread Tailor determines which threads should be combined based on only the number of executed cycles of each thread. Hence, the programs, whose threads change their computation loads according to program phases, may slow down with Thread Tailor. To solve this problem, we propose a method which dynamically recombines threads according to program phases for balancing the loads. The results of the experiment with SPLASH-2 benchmark suite and PARSEC benchmark suite show that the new method improves the execution time 6.0% in maximum.
Keywords :
microprocessor chips; multi-threading; chip multiprocessors; computation loads; efficient thread recombination; load balancing; processor specifications; program phase changes; program phases; thread tailor; Bandwidth; Benchmark testing; Instruction sets; Kernel; Load modeling; Memory management; Message systems; multi-core processors; multi-threading; thread scheduling;
Conference_Titel :
Networking and Computing (ICNC), 2012 Third International Conference on
Conference_Location :
Okinawa
Print_ISBN :
978-1-4673-4624-5
DOI :
10.1109/ICNC.2012.59