New Embedded Core Testing for System-on-Chips and System-in-Packages

Modern system-on-chip (SOC) and system-in-package (SiP) devices, together with deep submicron geometries, challenge the ability of traditional test methodologies. The accessibility to core terminals becomes critical, since direct physical access to some deeply embedded cores from chip pins is prohibitive or very complex. This paper presents a short survey of state-of-the-art test access mechanisms (TAM) and proposes a novel TAM scheme. The novel scheme is based on a concept of radio-on-chip technology. Specifically, by integrating very short-range low-power low cost (area) wireless network with embedded cores, the accessibility and transport capacity for test data and test response can be significantly improved. Simulation results based on test control distribution and resource partition are provided