Transaction Level Modeling for Early Verification on Embedded System Design

Time-to-market pressure and productivity gap are two factors that encourage the electronic design automation (EDA) industry and researcher of embedded system to enhance embedded system design method. Current embedded system design approach, register transfer level, is not sufficient to fulfill the embedded system design necessity. It needs a new design method above RTL, higher abstraction layer. Electronic system level is general term that used to name system above RTL. ESL definition so far is a system above RTL including hardware and software. In this paper we designed a transaction level modeling for early verification on embedded system design. This modeling is used to know functionality fulfillment at early stage. We specify four kind model for early verification purpose.