Notice of Violation of IEEE Publication Principles0.13μm CMOS DBS demodulator front-end using a 250MS/s 8 bit time interleaved pipeline ADC and a sampled loop filter PLL

Notice of Violation of IEEE Publication Principles

"A 0.13 μm CMOS DBS Demodulator Front-end Using a 250MS/s 8 bit Time Interleaved Pipeline ADC"
by A. Maxim, R. Poorfard, M. Chennam
in the Proceedings of the 2008 IEEE Radio and Wireless Symposium,
Page(s):53-56

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.

A low-IF satellite TV demodulator front-end for single-chip receiver SoC was realized in 0.13 mum CMOS using a low-power 0.25mm² 8b time interleaved pipeline ADC. A 250MS/s conversion rate was achieved by sharing the sample-and-hold amplifier (SHA) between two time interleaved ADCs having eight 1.5b cascaded stages. The full-rate SHA uses a feed-forward source follower to speed-up the settling by pre-charging the amplifier output at the voltage level sampled at its input. The ADC area was reduced by sharing the operational amplifiers between the time interleaved paths. The digi- al clock was generated with a sampled switched-capacitor loop filter PLL which reduces both reference and supply injected spurs. ADC\´s specifications include: INL plusmn2LSB, DNL plusmn0.5LSB, SFDR greater than 59dB, 35mW power dissipation, while the PLL achieves <20pspp total jitter and <-60dBc spurs.