Title :
Performance Evaluation and Optimization of Full Adders with Single-Electron Technology
Author :
Mao, Yanjie ; Chen, Chunhong
Author_Institution :
Dept. of Electr. Eng., Windsor Univ., Ont.
Abstract :
In this paper we present the full adder design considerations based on SET threshold logic, and show how the circuit performance depends upon its element parameters. In particular, an attempt is made to obtain the tradeoff between circuit delay/power and its reliability, where the reliability is measured by the maximum random background charges (RBC) that the circuit can tolerate while maintaining its correct logic operation
Keywords :
adders; logic design; optimisation; performance evaluation; single electron transistors; threshold logic; circuit delay; full adder design; maximum random background charge; optimization; performance evaluation; single-electron technology; threshold logic; Adders; Delay; Design optimization; Electrons; Equations; Logic circuits; Logic design; Logic devices; Logic gates; Virtual colonoscopy; SET; delay; full adder; reliability;
Conference_Titel :
Electrical and Computer Engineering, 2006. CCECE '06. Canadian Conference on
Conference_Location :
Ottawa, Ont.
Print_ISBN :
1-4244-0038-4
Electronic_ISBN :
1-4244-0038-4
DOI :
10.1109/CCECE.2006.277366
