Robust design of deep Sub-micron CMOS wireless SoC

Author

Hamada, Mototsugu ; Itoh, Nobuyuki

Author_Institution

Toshiba Corp, Tokyo

fYear

2008

fDate

22-24 Jan. 2008

Firstpage

61

Lastpage

64

Abstract

Scaled CMOS technology has opened the door of CMOS wireless SoC. The bright side is, apparently, high integration level and low cost implementation brought by the huge capacity of standard CMOS. However, as a designer point of view, another side should also be addressed, especially on PVT variation issues of scaled CMOS. In this paper, we will show the issues and their respective countermeasures on a voltage controlled oscillator in the local oscillator, a low noise amplifier and a channel select filter in the receiver, and digital calibration of I/Q mismatch in the transmitter.

Keywords

CMOS logic circuits; channel bank filters; logic design; low noise amplifiers; radio receivers; radio transmitters; radiofrequency integrated circuits; system-on-chip; voltage-controlled oscillators; PVT variation; channel select filter; deep submicron CMOS wireless SoC design; digital calibration; local oscillator; low noise amplifier; voltage controlled oscillator; CMOS technology; Circuits; Filters; Local oscillators; Low-noise amplifiers; Phase noise; Robustness; Transceivers; Voltage; Voltage-controlled oscillators; RFCMOS; robust design; scaled CMOS; variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Symposium, 2008 IEEE

Conference_Location

Orlando, FL

Print_ISBN

978-1-4244-1462-8

Electronic_ISBN

978-1-4244-1463-5

Type

conf

DOI

10.1109/RWS.2008.4463428

Filename

4463428