A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits

As CMOS technology is being scaled down aggressively towards the nano-regime, digital circuits are becoming more and more prone to failure, not only because of transient faults, but more likely as a result of permanent defects. This paper presents a new technique for defect-tolerance at the transistor level called transistor redundancy (TR); targeting the voter design in fault-tolerant systems. This is the first time transistor redundancy is used to design the first defect-tolerant voter circuit. TR allows the masking of faults resulting from permanent defects, since it uses redundant transistors to implement the functionality of each transistor. Circuit simulations of n-bit TR-voter based triple modular redundancy (TMR) adder were conducted and the results were compared with conventional-voter based TMR adder. The use of the proposed TR-voter gives 100% fault masking capabilities (considering the single fault scenario) compared to fault-intolerant conventional-voter that does not mask any defect. There was no increase in the time delay but the total number of transistor, for each adder, increased by 25% compared to conventional TMR