Application example of multi-level digital design verification by the SFG-tracing methodology

In this paper a novel methodology for the formal correctness verification of digital (VLSI) designs is presented. This methodology aims at bridging the gap from transistor switch level circuits, as obtained from circuit extraction, up to high level specifications. The SFG-tracing verification methodology inherits its power from the exploitation of the inherent algorithmic information in the high level (signal flow graph level) specifications. Given the fact that the circuit designer provides the appropriate reference signals and mapping functions, the methodology is intended to operate automatically on VLSI circuits of up to 50000 transistors and more.<>