DocumentCode
3139786
Title
Testing ASICs at-speed
Author
Gauthron, Christophe
Author_Institution
COMPASS Design Autom., San Jose, CA, USA
fYear
1991
fDate
27-31 May 1991
Firstpage
328
Lastpage
332
Abstract
At-speed test of ASICs is effective to detect delay faults, however, strobing is difficult because of process variations. In this paper two methodologies to generate at-speed test vectors are described. One is based on the comparison and merger of simulation traces obtained with different timing conditions. The other is a two-pass test approach.<>
Keywords
application specific integrated circuits; delays; digital integrated circuits; fault location; integrated circuit testing; ASICs; at-speed test vectors; delay faults; test vector generation; Application specific integrated circuits; Automatic testing; Circuit faults; Circuit testing; Clocks; Design automation; Fixtures; Propagation delay; System testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '91
Conference_Location
Paris, France
Print_ISBN
0-8186-2185-0
Type
conf
DOI
10.1109/EUASIC.1991.212843
Filename
212843
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