Serial concatenated trellis coded modulation with iterative decoding

We propose a design approach for serial concatenation of an outer convolutional code and an inner trellis code with multilevel amplitude/phase modulations using a bit-by-bit iterative decoding scheme. An example is given for throughput of 2 bits/sec/Hz with 2×8PSK modulation to clarify the approach. In this example, an 8-state outer code with rate 4/5 and a 2-state inner trellis code with 5 inputs and 2×8PSK outputs per trellis branch were used. The performance of this code with input block of 16384 bits is within 1.1 dB from the Shannon limit for 8PSK at a bit error probability of 5×10 ^-8 for 2 bits/sec/Hz with 10 iterations,