ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS project

Author

Jie, Liang

Author_Institution

Microelectronic Inst., Tech. Univ. Berlin, Germany

fYear

1991

fDate

27-31 May 1991

Firstpage

297

Lastpage

300

Abstract

The author describes a two ASICs design of a PCM 2 and 3-ary group multiplexer and demultiplexer based on the VENUS-S system. The ASIC chip set meets the requirements of multiplex equipment and is in accord with CCITT recommendations. A positive justification circuit had been adopted. HDB3 encoder/decoder and system fault alarm circuit are internal. Measurement of the system shows that the performance of the equipment which uses a MUX/DEMUX ASIC is better than the old one. Its power consumption is less than 14 W for 3-ary and 3.5 W for 2-ary.<>

Keywords

application specific integrated circuits; decoding; demultiplexing equipment; digital integrated circuits; encoding; multiplexing equipment; pulse-code modulation; 14 W; 2-ary type; 3-ary type; 3.5 W; ASIC chip set development; CCITT recommendations; EIS project; HDB3 encoder/decoder; VENUS-S system; demultiplexer; group MUX/DEMUX; multiplexer; positive justification circuit; system fault alarm circuit; Application specific integrated circuits; Circuit faults; Decoding; Digital communication; Microwave communication; Multiplexing; Optical signal processing; Partial response channels; Phase change materials; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '91

Conference_Location

Paris, France

Print_ISBN

0-8186-2185-0

Type

conf

DOI

10.1109/EUASIC.1991.212849

Filename

212849