Test generation using cross-observability calculations

Author

Cerny, E. ; Aboulhamid, E.M. ; Mauras, C. ; Rioux, P.

Author_Institution

Dept. d´´Inf. et de Recherche Operationnelle, Montreal Univ., Que., Canada

fYear

1991

fDate

27-31 May 1991

Firstpage

272

Lastpage

277

Abstract

The authors propose a symbolic algorithm for test generation of combinational circuits based on a sweep from the outputs to the inputs that calculates the relation between the values on the lines cut by this sweep along the way. The algorithm may generate the entire set of test vectors for a particular fault, or only a subset of this set, as required. A simple Boolean version of the algorithm is introduced to generate tests under the stuck-at-0/stuck-at-1 model and then a more complex version using multivalued logic is presented for generating tests for stuck-open faults in CMOS circuits.<>

Keywords

CMOS integrated circuits; combinatorial circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; Boolean version; CMOS circuits; combinational circuits; cross-observability calculations; fault model; multivalued logic; stuck-at-0/stuck-at-1 model; stuck-open faults; symbolic algorithm; test generation; test vectors; Binary decision diagrams; Boolean functions; Circuit faults; Circuit testing; Combinational circuits; Data structures; Logic testing; Multivalued logic; Observability; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '91

Conference_Location

Paris, France

Print_ISBN

0-8186-2185-0

Type

conf

DOI

10.1109/EUASIC.1991.212853

Filename

212853