A fast data path multiplier

Author

Priol, C. ; Magarshack, P.

Author_Institution

Thomson Composants Mil. et Spatiaux, Saint-Egreve, France

fYear

1991

fDate

27-31 May 1991

Firstpage

260

Lastpage

265

Abstract

The authors describe a highly configurable, compiled, fast data path multiplier implemented in the CSAM ASIC technology-independent library based on the GDT/GENESIL silicon compiler environments. The multiplier compiler, which allows independent control of the width of both operands, has been designed for use in high performance applications in data processing with a one stage pipeline option. The authors present the hardware organization combining the modified Booth decoding method and a tree algorithm to reduce the multiplication delay. It is the first time such a tree algorithm compiler is reported for the data path.<>

Keywords

application specific integrated circuits; circuit layout CAD; digital arithmetic; integrated logic circuits; logic CAD; multiplying circuits; pipeline processing; trees (mathematics); ASIC technology-independent library; CAD; CSAM; GDT; GENESIL; data processing; fast data path multiplier; hardware organization; modified Booth decoding method; multiplier compiler; one stage pipeline option; silicon compiler environments; tree algorithm compiler; Application specific integrated circuits; Data processing; Decoding; Delay; Hardware; Libraries; Silicon compiler; Trademarks; Tree graphs; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '91

Conference_Location

Paris, France

Print_ISBN

0-8186-2185-0

Type

conf

DOI

10.1109/EUASIC.1991.212855

Filename

212855