Title :
Implementation of a linear array element for matrix multiplication
Author :
Morante, M.A. ; De Quevedo, L. Saiz ; Tabuenca, P. ; Martinez, J.I. ; Villar, E.
Author_Institution :
Dept. of Electron., Cantabria Univ., Santander, Spain
Abstract :
The implementation of a linear array element for matrix multiplication is described. The cell corresponds to the fully pipelined model. First, its architecture and floorplan are described. Secondly, the design process is completed. Third, its area and time performances are analyzed and finally, the testing of the chips is carried out.<>
Keywords :
VLSI; application specific integrated circuits; logic testing; microprocessor chips; multiplying circuits; parallel architectures; parallel processing; pipeline processing; Eurochip; architecture; area performance; chip testing; design process; floorplan; fully pipelined model; linear array element; matrix multiplication; time performances; Broadcasting; Delay; Design methodology; Foundries; Performance analysis; Performance evaluation; Process design; Shift registers; Testing; Very large scale integration;
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
DOI :
10.1109/EUASIC.1991.212861
