VLSI design of an 8-bit fixed point CORDIC processor with extended operation set

Author

Metafas, Dimitris E. ; Krikis, George A. ; Goutis, Costas E.

Author_Institution

Dept. of Electr. Eng., Patras Univ., Greece

fYear

1991

fDate

27-31 May 1991

Firstpage

158

Lastpage

161

Abstract

An architecture of a DSP fixed point, pipelined processor is presented. It provides a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications. The processor architecture is based on the CORDIC and CCM algorithms and it is fully parallel and pipelined. An 8-bit fixed point chip has been designed using the VENUS-S semicustom design system in CMOS 1.5 mu m technology.<>

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; digital arithmetic; digital signal processing chips; 1.5 micron; 8 bit; CMOS; VENUS-S semicustom design system; VLSI; architecture; circular functions; convergence computing method; division; extended operation set; fixed point CORDIC processor; fixed point chip; high speed multiprocessor applications; hyperbolic functions; logarithm; multiplication; pipelined processor; processor architecture; set of elementary arithmetic operations; single hardware structure; square root; Arithmetic; CMOS technology; Convergence; Digital signal processing; Digital signal processing chips; Equations; Hardware; Iterative methods; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '91

Conference_Location

Paris, France

Print_ISBN

0-8186-2185-0

Type

conf

DOI

10.1109/EUASIC.1991.212874

Filename

212874