Synthesis and partitioning of standard cells for floorplan optimization

Glue logic of standard cells is partitioned into subsets to fill holes in a floorplan. This partitioning is driven by input constraints as the logic put in a hole has to depend on the inputs on the border of this hole. It has also to respect area ratio. The partitioning presented is prepared during factorization to allow an effective partitioning in terms of minimization of the crossing wires. This input driven partitioning method for Boolean networks consists of an adequate factorization step followed by a partitioning of factorized trees. The first step allows one to obtain easily partitionable trees for the partitioning algorithm.<>