Title :
Symbolic Simulation for Functional Verification with ADLIB and SDL
Author_Institution :
Stanford University, Stanford, CA
Abstract :
The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence of different levels of abstraction and asynchronous timing. This paper motivates interest in this problem and provides background information on verification, ADLIB, and SDL. It then discusses approaches for dealing with the problems encountered in the symbolic simulation of ADLIB/SDL descriptions.
Keywords :
Automatic control; Computational modeling; Computer simulation; Design methodology; Digital systems; Hardware design languages; LAN interconnection; Manuals; Registers; Timing;
Conference_Titel :
Design Automation, 1981. 18th Conference on
DOI :
10.1109/DAC.1981.1585336
