Title :
Processor chip design on submicron ASICs
Author_Institution :
IBM Labs., Boblingen, Germany
Abstract :
The processor chip set of the Low End ES/9000 is implemented on five CMOS VLSI Chips containing 2.8 Million transistors with an effective channel length of 0.5 mu m. The chips are packaged on multi-chip and single-chip modules. The worst case operating frequency is 35 MHz. The experience gained during the design of this processor is used to extrapolate into submicron technology down to 0.25 mu m. The result is the expectation of a tremendous density and performance increase within the next decade.<>
Keywords :
CMOS integrated circuits; application specific integrated circuits; microprocessor chips; multichip modules; 0.25 to 0.5 micron; 35 MHz; CMOS VLSI Chips; Low End ES/9000; MCM; density increase; effective channel length; performance increase; single chip modules; submicron ASICs; worst case operating frequency; Application specific integrated circuits; Automatic testing; Built-in self-test; CMOS process; CMOS technology; Chip scale packaging; Libraries; Logic design; Pins; Registers;
Conference_Titel :
Euro ASIC '91
Conference_Location :
Paris, France
Print_ISBN :
0-8186-2185-0
DOI :
10.1109/EUASIC.1991.212893
